The Physical Design Training is a 14 weeks course which has + 5 weeks for newbies and generally covers device fundamentals, timing concepts, advanced digital design, and UNIX. This is a course that is being structured for all the aspiring engineers to get in-depth knowledge of all the important aspects of physical design flow which will include floor planning, power planning, placement, scan chain reordering, global routing, and ECO.

The vlsi physical design engineer can be a part of any of the 4 main steps that are involved in Physical Design Training according to his qualification and the need of the industry. The steps include the following:

• Floorplanning: this is considered to be the very first step in the flow of physical design. It is the process where you need to identify the structures that are required to be placed close to each other and you need to allocate space for them in such a way that they can fulfill the goals of the space that is available, the performance that is required and the desire where you need everything to be close together. Depending on the area of design and its hierarchy, the floorplan is decided upon.
• Partitioning: this is a process wherein the chips will be divided into small blocks. The main reason as to why this is done is to separate out the different functional blocks. This will also be useful in making placement and routing much easier. This partitioning can be done in the RTL design phase where the design engineer will make partition of the entire design into sub-blocks and then will move ahead and design each module.
• Placement: placement usually makes use of RC values from the Virtual Route in order to calculate the timing. This placement is usually performed in optimization phases which include; Pre-Placement Optimization, In Placement Optimization, Post Placement Optimization before the clock tree synthesis and finally the Post Placement optimization which is carried out after the clock tree synthesis.
• The Clock Tree Synthesis: the main objective of the clock tree synthesis is to minimize the skew and insertion delay. After the clock tree synthesis, there should be an improvement in the hold slack. There are two types of top pins which are known as ignore pins and sync pins. In the clock tree optimization, the clock can be shielded so that the noise does not get coupled to any other signal. But with shielding, there is an increase in the area by 12% to 15%.

The physical design training Bangalore is a program that is well illustrated and has a great support with all the real-time examples from the industry. It also has 15+ assignments that cover various aspects of the physical design training implementation concepts which include the practical aspects. These assignments are so beneficial since they cover up most of the questions that are usually asked during an interview. They have various courses which include the Design Verification Courses, Online VLSI Courses, VLSI Backend Courses among the others out there.